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ds07-12517-2e fujitsu semiconductor data sheet 8-bit proprietary microcontroller cmos f 2 mc-8l mb89628r/629r/p629 mb89628r/629r/p629 n description the mb89628r/629r/p629 have been developed as a general-purpose version of the f 2 mc*-8l family consisting of proprietary 8-bit, single-chip microcontrollers. in addition to the f 2 mc-8l cpu core which can operate at low voltage but at high speed, the microcontrollers contain a variety of peripheral functions such as timers, serial interfaces, an a/d converter, and an external interrupt. the mb89628r/629r/p629 are applicable to a wide range of applications from welfare to industrial equipment, including portable devices. *: f 2 mc stands for fujitsu flexible microcontroller. n features ? large-size ram mb89p629: 4 kbytes mb89628r: 3 kbytes mb89629r: 3 kbytes ? high-speed processing at low voltage minimum execution time: 0.4 m s/3.5 v, 0.8 m s/2.7 v ?f 2 mc-8l family cpu core instruction set optimized for controllers (continued) n pac k ag e multiplication and division instructions 16-bit arithmetic operations test and branch instructions bit manipulation instructions, etc. (fpt-64p-m06) (dip-64p-m01) 64-pin plastic sh-dip 64-pin plastic qfp
2 mb89628r/629r/p629 (continued) ? four types of timers 8-bit pwm timer (also usable as a reload timer) 8-bit pulse width count timer (continuous measurement capable, applicable to remote control, etc.) 16-bit timer/counter 20-bit time-base timer ? two serial interfaces swichable the transfer direction allows communication with various equipment. ?8-bit a/d converter sense mode function enabling comparison at 5 m s activation by an external input capable ? external interrupt: 4 channels four channels are independent and capable of wake-up from low-power consumption modes (with an edge detection function). ? low-power consumption modes stop mode (oscillation stops to reduce the current consumption.) sleep mode (the cpu stops to reduce the current consumption to approx. 1/3 of normal.)
3 mb89628r/629r/p629 n product lineup *1: the piggyback/evaluation product is applicable to the mb89620 series. *2: varies with conditions such as the operating frequency. (see section n electrical characteristics.) in the case of the mb89pv620, the voltage varies with the restrictions of the eprom for use. mb89629r mb89p629 mb89pv620 *1 classification mass production products (mask rom products) one-time prom product for evaluation and development piggyback/evaluation product for evaluation and development rom size 24 k 8 bits (internal mask rom) 32 k 8 bits (internal mask rom) 32 k 8 bits (internal prom, programming with general-purpose eprom programmer) 32 k 8 bits (external rom) ram size 3072 8 bits 4096 8 bits 1 k 8 bits cpu functions number of instructions: 136 instruction bit length: 8 bits instruction length: 1 to 3 bytes data bit length: 1, 8, 16 bits minimum execution time: 0.4 m s/10 mhz interrupt processing time: 3.6 m s/10 mhz ports input ports: 5 (4 ports also serve as peripherals.) output ports (n-ch open-drain): 8 (all also serve as peripherals.) i/o ports (n-ch open-drain): 8 (4 ports also serve as peripherals.) output ports (cmos): 8 i/o ports (cmos): 24 to t a l : 5 3 8-bit pwm timer 8-bit reload timer operation (toggled output capable, operating clock cycle: 0.4 m s to 3.3 ms) 8-bit resolution pwm operation (conversion cycle: 102 m s to 839 ms) 8-bit pulse width count timer 8-bit timer operation (overflow output capable, operating clock cycle: 0.4 to 12.8 m s) 8-bit reload timer operation (toggled output capable, operating clock cycle: 0.4 to 12.8 m s) 8-bit pulse width measurement operation (continuous measurement h pulse width/l pulse width/from - to - /from to capable) 16-bit timer/counter 16-bit timer operation (operating clock cycle: 0.4 m s) 16-bit event counter operation (rising/falling/both edges selectability) 8-bit serial i/o 1, 8-bit serial i/o 2 8-bits lsb first/msb first transfer selectability one clock selectable from four transfer clocks (one external shift clock, three internal shift clocks: 0.8 m s, 3.2 m s, 12.8 m s) 8-bit a/d converter 8-bit resolution 8 channels a/d conversion mode (conversion time: 18 m s) sense mode (conversion time: 5 m s) continuous activation by an external activation or an internal timer capable reference voltage input external interrupt 4 independent channels (edge selection, interrupt vector, source flag) rising edge/falling edge selectability used also for wake-up from stop/sleep mode. (edge detection is also permitted in stop mode.) standby modes sleep mode, stop mode process cmos operating voltage *2 2.2 v to 6.0 v 2.7 v to 6.0 v eprom for use mb89628r mbm27c256a-20 part number parameter
4 mb89628r/629r/p629 n package and corresponding products : available : not available note: for more information about each package, see section n package dimensions. n differences among products 1. memory size before evaluating using the piggyback product, verify its differences from the product that will actually be used. take particular care on the following points: ? on the mb89p629, the program area starts from address 8007 h but on the mb89pv620, mb89628r, and mb89629r starts from 8000 h . (on the mb89p629, addresses 8000 h to 8006 h comprise the option setting area, option settings can be read by reading these addresses. on the mb89pv620, mb89628r, and mb89629r, addresses 8000 h to 8006 h could also be used as a program rom. however, do not use these addresses in order to maintain compatibility of the mb89p629.) 2. current consumption ? in the case of the mb89pv620, add the current consumed by the eprom which is connected to the top socket. ? when operated at low speed, the product with an otprom (one-time prom) or an eprom will consume more current than the product with a mask rom. however, the current consumption in sleep/stop modes is the same. (for more information, see section n electrical characteristics.) 3. mask options functions that can be selected as options and how to designate these options vary by the product. before using options check section n mask options. take particular care on the following points: ? a pull-up resistor cannot be set for p40 to p47 on the mb89p629. ? a pull-up resistor is not selected for p50 to p57 when the a/d converter is used. ? options are fixed on the mb89pv620. package mb89628r mb89629r mb89p629 mb89pv620 dip-64p-m01 fpt-64p-m06 mdp-64c-p02 mqp-64c-p01
5 mb89628r/629r/p629 n pin assignment (dip-64p-m01) (top view) 1 p36/wto 2 p37/pto 3 p40 4 p41 5 p42 6 p43 7 p44/bz 8 p45/sck2 9 p46/so2 10 p47/si2 11 p50/an0 12 p51/an1 13 p52/an2 14 p53/an3 15 p54/an4 16 p55/an5 17 p56/an6 18 p57/an7 19 av cc 20 avr 21 av ss 22 p60/int0 23 p61/int1 24 p62/int2 25 p63/int3 26 p64 27 rst 28 mod0 29 mod1 30 x0 31 x1 32 v ss v cc 64 p35/pwc 63 p34/ec 62 p33/si1 61 p32/so1 60 p31/sck1 59 p30/adst/clko 58 v ss 57 p00 56 p01 55 p02 54 p03 53 p04 52 p05 51 p06 50 p07 49 p10 48 p11 47 p12 46 p13 45 p14 44 p15 43 p16 42 p17 41 p20 40 p21 39 p22 38 p23 37 p24 36 p25 35 p26 34 p27 33 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 p45/sck2 p46/so2 p47/si2 p50/an0 p51/an1 p52/an2 p53/an3 p54/an4 p55/an5 p56/an6 p57/an7 av cc avr av ss p60/int0 p61/int1 p62/int2 p63/int3 p64 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 p30/adst/clko v ss p00 p01 p02 p03 p04 p05 p06 p07 p10 p11 p12 p13 p14 p15 p16 p17 p20 64 63 62 61 60 59 58 57 56 55 54 53 52 p44/bz p43 p42 p41 p40 p37/pto p36/wto v cc p35/pwc p34/ec p33/si1 p32/so1 p31/sck1 20 21 22 23 24 25 26 27 28 29 30 31 32 rst mod0 mod1 x0 x1 v ss p27 p26 p25 p24 p23 p22 p21 (fpt-64p-m06) (top view)
6 mb89628r/629r/p629 n pin description (continued) *1: dip-64p-m01 *2: fpt-64p-m06 pin no. pin name circuit type function sh-dip *1 qfp *2 30 23 x0 a cystal oscillator pins 31 24 x1 28 21 mod0 b operating mode selection pins connect directly to v cc or v ss . 29 22 mod1 27 20 rst c reset i/o pin this pin is an n-ch open-drain output type with a pull-up resistor, and a hysteresis input type. l is output from this pin by an internal reset source. the internal circuit is initialized by the input of l. 56 to 49 49 to 42 p00 to p07 d general-purpose i/o ports 48 to 41 41 to 34 p10 to p17 d 40, 39 33, 32 p20, p21 f general-purpose output-only ports 38, 37 31, 30 p22, p23 d 36 to 33 29 to 26 p24 to p27 f 58 51 p30/adst/ clko e general-purpose i/o port also serves as an a/d converter external activation and an oscillation monitor clock output. this port is a hysteresis input type. 59 52 p31/sck1 e general-purpose i/o port also serves as the clock i/o for the 8-bit serial i/o 1. this port is a hysteresis input type. 60 53 p32/so1 e general-purpose i/o port also serves as the data output for the 8-bit serial i/o 1. this port is a hysteresis input type. 61 54 p33/si1 e general-purpose i/o port also serves as the data input for the 8-bit serial i/o 1. this port is a hysteresis input type. 62 55 p34/ec e general-purpose i/o port also serves as the external clock input for the 16-bit timer/ counter. this port is a hysteresis input type. 63 56 p35/pwc e general-purpose i/o port also serves as the measured pulse input for the 8-bit pulse width count timer. this port is a hysteresis input type. 1 58 p36/wto e general-purpose i/o port also serves as the toggle output for the 8-bit pulse width count timer. this port is a hysteresis input type.
7 mb89628r/629r/p629 (continued) *1: dip-64p-m01 *2: fpt-64p-m06 pin no. pin name circuit type function sh-dip *1 qfp *2 2 59 p37/pto e general-purpose i/o port also serves as the toggle output for the 8-bit pwm timer. this port is a hysteresis input type. 3 to 6 60 to 63 p40 to p43 g n-ch open-drain i/o ports these ports are a hysteresis input type. 7 64 p44/bz g n-ch open-drain i/o port also serves as a buzzer output. this port is a hysteresis input type. 8 1 p45/sck2 g n-ch open-drain i/o port also serves as the clock i/o for the 8-bit serial i/o 2. this port is a hysteresis input type. 9 2 p46/so2 g n-ch open-drain i/o port also serves as the data output for the 8-bit serial i/o 2. this port is a hysteresis input type. 10 3 p47/si2 g n-ch open-drain i/o port also serves as the data input for the 8-bit serial i/o 2. this port is a hysteresis input type. 11 to 18 4 to 11 p50/an0 to p57/an7 h n-ch open-drain output-only port also serves as the analog input for the a/d converter. 22 to 25 15 to 18 p60/int0 to p63/int2 i general-purpose input-only ports also serve as an external interrupt input. these ports are a hysteresis input type. 26 19 p64 i general-purpose input-only port this port is a hysteresis input type. 64 57 v cc power supply pin 32, 57 25, 50 v ss power supply (gnd) pins 19 12 av cc a/d converter power supply pin 20 13 avr a/d converter reference voltage input pin 21 14 av ss a/d converter power supply (gnd) pin. use this pin at the same voltage as v ss .
8 mb89628r/629r/p629 n i/o circuit type (continued) type circuit remarks a ? at an oscillation feedback resistor of approximately 1 m w /5.0 v b c ? at an output pull-up resistor (p-ch) of approximately 50 m w /5.0 v ? cmos hysteresis input d ? cmos output ? cmos input ? pull-up resistor optional (except p22 and p23) e ? cmos output ? hysteresis input ? pull-up resistor optional f ? cmos output x1 x0 standby control signal r p-ch n-ch p-ch n-ch r p-ch p-ch n-ch r p-ch p-ch n-ch
9 mb89628r/629r/p629 (continued) type circuit remarks g ? n-ch open-drain output ? hysteresis input ? pull-up resistor optional (mb89628r and mb89629r only) h ? n-ch open-drain output ? analog input i ? hysteresis input ? pull-up resistor optional n-ch r p-ch p-ch analog input n-ch r p-ch r
10 mb89628r/629r/p629 n handling devices 1. preventing latchup latchup may occur on cmos ics if voltage higher than v cc or lower than v ss is applied to input and output pins other than medium- to high-voltage pins or if higher than the voltage which shows on 1. absolute maximum ratings in section n electrical characteristics is applied between v cc and v ss . when latchup occurs, power supply current increases rapidly and might thermally damage elements. when using, take great care not to exceed the absolute maximum ratings. also, take care to prevent the analog power supply (av cc and avr) and analog input from exceeding the digital power supply (v cc ) when the analog system power supply is turned on and off. 2. treatment of unused input pins leaving unused input pins open could cause malfunctions. they should be connected to a pull-up or pull-down resistor. 3. treatment of power supply pins on microcontrollers with a/d and d/a converters connect to be av cc = davc = v cc and av ss = avr = v ss even if the a/d and d/a converters are not in use. 4. treatment of n.c. pins be sure to leave (internally connected) n.c. pins open. 5. power supply voltage fluctuations although v cc power supply voltage is assured to operate within the rated range, a rapid fluctuation of the voltage could cause malfunctions, even if it occurs within the rated range. stabilizing voltage supplied to the ic is therefore important. as stabilization guidelines, it is recommended to control power so that v cc ripple fluctuations (p-p value) will be less than 10% of the standard v cc value at the commercial frequency (50 to 60 hz) and the transient fluctuation rate will be less than 0.1 v/ms at the time of a momentary fluctuation such as when power is switched. 6. precautions when using an external clock even when an external clock is used, oscillation stabilization time is required for power-on reset (optional) and wake-up from stop mode.
11 mb89628r/629r/p629 n programming to the eprom on the mb89p629 the mb89p629 is an otprom version of the mb89628r and mb89629r. 1. features ? 16-kbyte prom on chip ? options can be set using the eprom programmer. ? equivalency to the mbm27c256a in eprom mode (when programmed with the eprom programmer) 2. memory space memory space in eprom mode, option area is diagrammed below. 3. programming to the eprom in eprom mode, the mb89p629 functions equivalent to the mbm27c256a. this allows the prom to be programmed with a general-purpose eprom programmer (the electronic signature mode cannot be used) by using the dedicated socket adapter. ? programming procedure (1) set the eprom programmer to the mbm27c256a. (2) load program data into the eprom programmer at 0000 h to 7fff h (note that addresses 8000 h to ffff h while operating as a single chip assign to 0000 h to 7fff h in eprom mode. for information about each corresponding option, see 7. setting otprom options.) (3) program to 0000 h to 7fff h with the eprom programmer. program area (eprom) 32 kb 7fff h 0000 h option area option area 0007 h 0000 h address 0080 h 0100 h 0200 h 8000 h single chip i/o ram register prom 32 kb not available 1080 h 8007 h ffff h eprom mode (corresponding addresses on the eprom programmer)
12 mb89628r/629r/p629 4. recommended screening conditions high-temperature aging is recommended as the pre-assembly screening procedure for a product with a blanked otprom microcomputer program. 5. programming yield all bits cannot be programmed at fujitsu shipping test to a blanked otprom microcomputer, due to its nature. for this reason, a programming yield of 100% cannot be assured at all times. 6. eprom programmer socket adapter inquiry: sun hayato co., ltd.: tel 81-3-3802-5760 package compatible socket adapter dip-64p-m01 rom-64sd-28dp-8l fpt-64p-m06 rom-64qf-28dp-8l program, verify aging +150?, 48 hrs. data verification assembly
13 mb89628r/629r/p629 7. setting otprom options the programming procedure is the same as that for the prom. options can be set by programming values at the addresses shown on the memory map. the relationship between bits and options is shown on the following bit map: ? otprom option bit map notes: ? set each bit to 1 to erase. ? do not write 0 to the vacant bit. the read value of the vacant bit is 1, unless 0 is written to it. ? always write 0 to the reserved bit. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 8000 h (0000 h ) vacancy readable and writable vacancy readable and writable vacancy readable and writable oscillation stabilization time 1: crystal 0: ceramic reset pin output 1: yes 2: no power-on reset 1: yes 0: no vacancy readable and writable vacancy readable and writable 8001 h (0001 h ) p07 pull-up 1: no 0: yes p06 pull-up 1: no 0: yes p05 pull-up 1: no 0: yes p04 pull-up 1: no 0: yes p03 pull-up 1: no 0: yes p02 pull-up 1: no 0: yes p01 pull-up 1: no 0: yes p00 pull-up 1: no 0: yes 8002 h (0002 h ) p17 pull-up 1: no 0: yes p16 pull-up 1: no 0: yes p15 pull-up 1: no 0: yes p14 pull-up 1: no 0: yes p13 pull-up 1: no 0: yes p12 pull-up 1: no 0: yes p11 pull-up 1: no 0: yes p10 pull-up 1: no 0: yes 8003 h (0003 h ) p37 pull-up 1: no 0: yes p36 pull-up 1: no 0: yes p35 pull-up 1: no 0: yes p34 pull-up 1: no 0: yes p33 pull-up 1: no 0: yes p32 pull-up 1: no 0: yes p31 pull-up 1: no 0: yes p30 pull-up 1: no 0: yes 8004 h (0004 h ) p57 pull-up 1: no 0: yes p56 pull-up 1: no 0: yes p55 pull-up 1: no 0: yes p54 pull-up 1: no 0: yes p53 pull-up 1: no 0: yes p52 pull-up 1: no 0: yes p51 pull-up 1: no 0: yes p50 pull-up 1: no 0: yes 8005 h (0005 h ) vacancy readable and writable vacancy readable and writable vacancy readable and writable p64 pull-up 1: no 0: yes p63 pull-up 1: no 0: yes p62 pull-up 1: no 0: yes p61 pull-up 1: no 0: yes p60 pull-up 1: no 0: yes 8006 h (0006 h ) vacancy readable and writable vacancy readable and writable vacancy readable and writable vacancy readable and writable vacancy readable and writable vacancy readable and writable vacancy readable and writable reserved bit readable and writable
14 mb89628r/629r/p629 n programming to the eprom with piggyback/evaluation device 1. eprom for use mbm27c256a-20tv, mbm27c256a-20cz 2. programming socket adapter to program to the prom using an eprom programmer, use the socket adapter (manufacturer: sun hayato co., ltd.) listed below. inquiry: sun hayato co., ltd.: tel 81-3-3802-5760 3. memory space memory space in 32-kbyte prom on the eprom programmer is diagrammed below. 4. programming to the eprom (1) set the eprom programmer to the mbm27c256a. (2) load program data into the eprom programmer at 0007 h to 7fff h . (3) program to 0000 h to 7fff h with the eprom programmer. package adapter socket part number lcc-32 (rectangle) rom-32lc-28dp-yg 0000 h 0080 h 0480 h 8000 h 8007 h ffff h 0000 h 0007 h 7fff h i/o ram not available not available prom 32 kb not available eprom 32 kb single chip corresponding addresses on the eprom programmer address
15 mb89628r/629r/p629 n block diagram x0 x1 oscillator rst clock controller reset circuit (wdt) 8 8 p00 to p07 p10 to p17 cmos i/o port external bus interface mod0 mod1 p20 to p27 cmos output port ram f 2 mc-8l cpu rom v cc , v ss 2 other pins 20-bit time-base timer 8-bit pwm timer 8-bit pulse width count timer 16-bit timer/counter 8-bit serial i/o 1 cmos i/o port buzzer output n-ch open-drain output port 8-bit a/d converter 4 4 external interrupt input port p60/int0 to p63/int3 8 p64 avr av cc av ss 8 p50/an0 to p57/an7 p40 to p43 p44/bz p45/sck2 p46/so2 p47/si2 p30/adst/clko p31/sck1 p32/so1 p33/si1 p34/ec p35/pwc p36/wto p37/pto 8 4 port 0 and port 1 port 2 internal bus 8-bit serial i/o 2 n-ch open-drain i/o port port 3 port 4 port 5 port 6
16 mb89628r/629r/p629 n cpu core 1. memory space the microcontrollers of the mb89628r/629r/p629 offer a memory space of 64 kbytes for storing all of i/o, data, and program areas. the i/o area is located at the lowest address. the data area is provided immediately above the i/o area. the data area can be divided into register, stack, and direct areas according to the application. the program area is located at exactly the opposite end, that is, near the highest address. provide the tables of interrupt reset vectors and vector call instructions toward the highest address within the program area. the memory space of the mb89628r/629r/p629 is structured as illustrated below. memory space *1: the internal ram of the mb89pv620 is 1 kbyte. the ram of a development tool can be substituted for that ram when the tool is connected. if the mb89pv620 is used as a piggyback product, however, it runs out of ram. note, in addition, that some tools such as the mb2140 series cannot be used due to mapping restrictions. *2: since addresses 8000 h to 8006 h for the mb89p629 comprise an option area, do not use this area for the mb89pv620, mb89628r, and mb89629r. 0000 h 0080 h 0100 h 0480 h 8000 h mb89pv620 i/o ram * 1 register external area external rom 32 kb 0000 h 0080 h 0100 h 0200 h a000 h i/o ram 3 kb register rom 24 kb 0000 h 0080 h 0100 h 0200 h 8000 h 8007 h mb89p629 i/o ram 4 kb register rom 32 kb ffff h not available not available option area * 2 0c80 h 0200 h 0000 h 0080 h 0100 h 0200 h 8000 h i/o ram 3 kb register rom 32 kb not available 0c80 h mb89629r ffff h ffff h ffff h mb89628r 1080 h 1 kb
17 mb89628r/629r/p629 3. registers the f 2 mc-8l family has two types of registers; dedicated registers in the cpu and general-purpose registers in the memory. the following dedicated registers are provided: program counter (pc): a 16-bit register for indicating instruction storage positions accumulator (a): a 16-bit temporary register for storing arithmetic operations, etc. when the instruction is an 8-bit data processing instruction, the lower byte is used. temporary accumulator (t): a 16-bit register which performs arithmetic operations with the accumulator when the instruction is an 8-bit data processing instruction, the lower byte is used. index register (ix): a 16-bit register for index modification extra pointer (ep): a 16-bit pointer for indicating a memory address stack pointer (sp): a 16-bit register for indicating a stack area program status (ps): a 16-bit register for storing a register pointer, a condition code the ps can further be divided into higher 8 bits for use as a register bank pointer (rp) and the lower 8 bits for use as a condition code register (ccr). (see the diagram below.) pc a t ix ep sp ps 16 bits : program counter : accumulator : temporary accumulator : index register : extra pointer : stack pointer : program status fffd h undefined undefined undefined undefined undefined i-flag = 0, il1, 0 = 11 other bits are undefined. initial value structure of the program status register vacancy vacancy vacancy h i il1, 0 n z vc 54 rp ps 109876 3210 15 14 13 12 11 rp ccr
18 mb89628r/629r/p629 the rp indicates the address of the register bank currently in use. the relationship between the pointer contents and the actual address is based on the conversion rule illustrated below. the ccr consists of bits indicating the results of arithmetic operations and the contents of transfer data and bits for control of cpu operations at the time of an interrupt. h-flag: set when a carry or a borrow from bit 3 to bit 4 occurs as a result of an arithmetic operation. cleared otherwise. this flag is for decimal adjustment instructions. i-flag: interrupt is allowed when this flag is set to 1. interrupt is prohibited when the flag is set to 0. set to 0 when reset. il1, 0: indicates the level of the interrupt currently allowed. processes an interrupt only if its request level is higher than the value indicated by this bit. n-flag: set if the msb is set to 1 as the result of an arithmetic operation. cleared when the bit is set to 0. z-flag: set when an arithmetic operation results in 0. cleared otherwise. v-flag: set if the complement on 2 overflows as a result of an arithmetic operation. reset if the overflow does not occur. c-flag: set when a carry or a borrow from bit 7 occurs as a result of an arithmetic operation. cleared otherwise. set to the shift-out value in the case of a shift instruction. il1 il0 interrupt level high-low 00 1 high low = no interrupt 01 10 2 11 3 rule for conversion of actual addresses of the general-purpose register area ? a15 ? a14 ? a13 ? a12 ? a11 ? a10 ? a9 ? a8 r4 a7 r3 a6 r2 a5 r1 a4 r0 a3 b2 a2 b1 a1 b0 a0 lower op codes rp generated addresses
19 mb89628r/629r/p629 the following general-purpose registers are provided: general-purpose registers: an 8-bit register for storing data the general-purpose registers are 8 bits and located in the register banks of the memory. one bank contains eight registers and up to a total of 32 banks can be used on the mb89628r and mb89629r. the bank currently in use is indicated by the register bank pointer (rp). register bank configuration r 1 r 2 r 3 r 4 r 5 r 6 r 7 this address = 0100 h + 8 (rp) memory area 32 banks r 0
20 mb89628r/629r/p629 n i/o map (continued) address read/write register name register description 00 h (r/w) pdr0 port 0 data register 01 h (w) ddr0 port 0 data direction register 02 h (r/w) pdr1 port 1 data register 03 h (w) ddr1 port 1 data direction register 04 h (r/w) pdr2 port 2 data register 05 h (r/w) bctr external bus pin control register 06 h vacancy 07 h vacancy 08 h (r/w) stbc standby control register 09 h (r/w) wdtc watchdog timer control register 0a h (r/w) tbtc time-base timer control register 0b h vacancy 0c h (r/w) pdr3 port 3 data register 0d h (w) ddr3 port 3 data direction register 0e h (r/w) pdr4 port 4 data register 0f h (r/w) bzcr buzzer register 10 h (r/w) pdr5 port 5 data register 11 h (r) pdr6 port 6 data register 12 h (r/w) cntr pwm control register 13 h (w) comr pwm compare register 14 h (r/w) pcr1 pwc pulse width control register 1 15 h (r/w) pcr2 pwc pulse width control register 2 16 h (r/w) rlbr pwc reload buffer register 17 h vacancy 18 h (r/w) tmcr 16-bit timer control register 19 h (r/w) tchr 16-bit timer count register (h) 1a h (r/w) tclr 16-bit timer count register (l) 1b h vacancy 1c h (r/w) smr1 serial i/o 1 mode register 1d h (r/w) sdr1 serial i/o 1 data register 1e h (r/w) smr2 serial i/o 2 mode register 1f h (r/w) sdr2 serial i/o 2 data register
21 mb89628r/629r/p629 (continued) note: do not use vacancies. address read/write register name register description 20 h (r/w) adc1 a/d converter control register 1 21 h (r/w) adc2 a/d converter control register 2 22 h (r/w) adcd a/d converter data register 23 h vacancy 24 h (r/w) eic1 external interrupt control register 1 25 h (r/w) eic2 external interrupt control register 2 26 h (r/w) clke clock output control register 27 h to 7b h vacancy 7c h (w) ilr1 interrupt level setting register 1 7d h (w) ilr2 interrupt level setting register 2 7e h (w) ilr3 interrupt level setting register 3 7f h vacancy
22 mb89628r/629r/p629 n electrical characteristics 1. absolute maximum ratings (av ss = v ss = 0.0 v) *1: use av cc and v cc set at the same voltage. take care so that av cc does not exceed v cc , such as when power is turned on. *2: v i and v o must not exceed v cc + 0.3 v. precautions: permanent device damage may occur if the above absolute maximum ratings are exceeded. functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. exposure to absolute maximum rating conditions for extended periods may affect device reliability. parameter symbol value unit remarks min. max. power supply voltage v cc av cc v ss C 0.3 v ss + 7.0 v * 1 a/d converter reference input voltage avr v ss C 0.3 v ss + 7.0 v avr must not exceed av cc + 0.3 v. input voltage v i v ss C 0.3 v cc + 0.3 v except p40 to p47* 2 v i2 v ss C 0.3 v ss + 7.0 v p40 to p47 output voltage v o v ss C 0.3 v cc + 0.3 v except p40 to p47* 2 v o2 v ss C 0.3 v ss + 7.0 v p40 to p47 l level maximum output current i ol ? 20 ma l level average output current i olav ? 4ma average value (operating current operating rate) l level total maximum output current ? i ol ? 100 ma l level total average output current ? i olav ? 40 ma average value (operating current operating rate) h level maximum output current i oh ? C20 ma h level average output current i ohav ? C4 ma average value (operating current operating rate) h level total maximum output current ? i oh ? C50 ma h level total average output current ? i ohav ? C20 ma average value (operating current operating rate) power consumption p d ? 300 mw operating temperature t a C40 +85 c storage temperature tstg C55 +150 c
23 mb89628r/629r/p629 2. recommended operating conditions (av ss = v ss = 0.0 v) * : these values vary with the operating frequency and analog assurance range. see figure 1 and 5. a/d converter electrical characteristics. figure 1 operating voltage vs. clock operating frequency figure 1 indicates the operating frequency of the external oscillator at an instruction cycle of 4/f c . parameter symbol value unit remarks min. max. power supply voltage v cc av cc 2.2* 6.0* v normal operation assurance range* (mb89628r/629r) 2.7* 6.0* v normal operation assurance range* (mb89p629/pv620) 1.5 6.0 v retains the ram state in stop mode a/d converter reference input voltage avr 0.0 av cc v operating temperature t a C40 +85 c 1 2 3 4 5 6 1.0 10.0 operation assurance range 5.0 clock operating frequency (at an instruction cycle of 4/fc) (mhz) note: 2.0 3.0 4.0 6.0 7.0 8.0 9.0 analog accuracy assured in the av cc = v cc = 3.5 v to 6.0 v range 4.0 2.0 0.8 0.4 minimum execution time (instruction cycle) ( m s) operating voltage (v) the shaded area is assured only for the mb89628r/629r.
24 mb89628r/629r/p629 3. dc characteristics (av cc = v cc = +5.0 v, av ss = v ss = 0.0 v, t a = C40 c to +85 c) (continued) parameter symbol pin condition value unit remarks min. typ. max. h level input voltage v ih p00 to p07, p10 to p17, p22, p23 ? 0.7 v cc ? v cc + 0.3 v v ihs rst , mod0, mod1, p30 to p37, p60 to p64 ? 0.8 v cc ? v cc + 0.3 v v ihs2 p40 to p47 ? 0.8 v cc ? v ss + 6.0 v l level input voltage v il p00 to p07, p10 to p17, p22, p23 ? v ss - 0.3 ? 0.3 v cc v v ils rst , mod0, mod1, p30 to p37, p40 to p47, p60 to p64 v ss - 0.3 ? 0.2 v cc v open-drain output pin application voltage v d p50 to p57 v ss - 0.3 ? v ss + 0.3 v v d2 p40 to p47 ? v ss - 0.3 ? v ss + 6.0 v h level output voltage v oh p00 to p07, p10 to p17, p20 to p27, p30 to p37 i oh = C2.0 ma 4.0 ?? v l level output voltage v ol p00 to p07, p10 to p17, p20 to p27, p30 to p37, p40 to p47, p50 to p57 i ol = +4.0 ma ?? 0.4 v v ol2 rst 0.4v input leakage current (hi-z output leakage current) i li1 p00 to p07, p10 to p17, p20 to p27, p30 to p37, p40 to p47, p60 to p64, mod0, mod1 0.0 v < v i < v cc ?? 5 m a without pull-up resistor pull-up resistance r pull p00 to p07, p10 to p17, p30 to p37, p40 to p47, p50 to p57, p60 to p64, rst v i = 0.0 v 25 50 100 k w
25 mb89628r/629r/p629 (continued) (av cc = v cc = +5.0 v, av ss = v ss = 0.0 v, t a = C40 c to +85 c) * : in the case of the mb89pv620, the current consumed by the connected eprom and ice is not included. the power supply current is measured at the external clock. parameter symbol pin condition value unit remarks min. typ. max. power supply current* i cc v cc f c = 10 mhz normal operation mode (external clock) 915ma mb89628r, mb89629r 10 18 ma mb89p629 i ccs f c = 10 mhz sleep mode (external clock) 3 4ma i cch stop mode t a = +25 c 1 m a i a av cc f c = 10 mhz, when a/d conversion is activated 1 3ma i ah f c = 10 mhz, t a = +25 c, when a/d conversion is stopped 1 m a input capacitance c in other than av cc , av ss , v cc , and v ss f = 1 mhz 10 pf
26 mb89628r/629r/p629 4. ac characteristics (1) reset timing (v cc = +5.0 v 10%, av ss = v ss = 0.0 v, t a = C40 c to +85 c) note: t xcyl is the oscillation cycle (1/f c ) to input to the x0 pin. (2) power-on reset (av ss = v ss = 0.0 v, t a = C40 c to +85 c) note: make sure that power supply rises within the selected oscillation stabilization time. if power supply voltage needs to be varied in the course of operation, a smooth voltage rise is recommended. parameter symbol condition value unit remarks min. max. rst l pulse width t zlzh 16 t xcyl ns parameter symbol condition value unit remarks min. max. power supply rising time t r 50 ms power-on reset function only power supply cut-off time t off 1 ms due to repeated operations 0.2 v cc 0.2 v cc rst t zlzh 0.2 v 0.2 v 2.0 v v cc 0.2 v t r t off
27 mb89628r/629r/p629 (3) clock timing (av ss = v ss = 0.0 v, t a = C40 c to +85 c) (4) instruction cycle parameter symbol pin condition value unit remarks min. max. clock frequency f c x0, x1 110mhz clock cycle time t xcyl x0, x1 100 1000 ns input clock pulse width p wh p wl x0 20 ns external clock input clock rising/falling time t cr t cf x0 10 ns external clock parameter symbol value (typical) unit remarks instruction cycle (minimum execution time) t inst 4/f c m s t inst = 0.4 m s when operating at f c = 10 mhz x0 and x1 timing and conditions 0.2 v cc 0.8 v cc x0 0.2 v cc t cr t cf 0.8 v cc 0.2 v cc x0 x1 x0 x1 when a crystal or ceramic resonator is used when an external clock is used open t xcyl p wh p wl clock conditions
28 mb89628r/629r/p629 (5) serial i/o timing (v cc = +5.0 v 10%, av ss = v ss = 0.0 v, t a = C40 c to +85 c) * : for information on t inst , see (4) instruction cycle. parameter symbol pin condition value unit remarks min. max. serial clock cycle time t scyc sck1, sck2 internal shift clock mode 2 t inst * m s sck1 ? so1 time sck2 ? so2 time t slov sck1, so1 sck2, so2 C200 200 ns valid si1 ? sck1 - valid si2 ? sck2 - t ivsh si1, sck1 si2, sck2 1/2 t inst * m s sck1 - ? valid si1 hold time sck2 - ? valid si2 hold time t shix sck1, si1 sck2, si2 1/2 t inst * m s serial clock h pulse width t shsl sck1, sck2 external shift clock mode 1 t inst * m s serial clock l pulse width t slsh sck1, sck2 1 t inst * m s sck1 ? so1 time sck2 ? so2 time t slov sck1, so1 sck2, so2 0200ns valid si1 ? sck1 - valid si2 ? sck2 - t ivsh si1, sck1 si2, sck2 1/2 t inst * m s sck1 - ? valid si1 hold time sck2 - ? valid si2 hold time t shix sck1, si1 sck2, si2 1/2 t inst * m s
29 mb89628r/629r/p629 internal shift clock mode external shift clock mode 0.8 v 2.4 v t scyc 2.4 v t slov 0.2 v cc t shix 0.8 v 0.8 v t ivsh 0.8 v cc 0.2 v cc 0.8 v cc sck1 so1 si1 sck2 so2 si2 t slsh 2.4 v t slov 0.2 v cc t shix 0.8 v cc 0.8 v t ivsh 0.8 v cc 0.2 v cc 0.8 v cc sck1 so1 si1 sck2 so2 si2 t shsl 0.8 v cc 0.2 v cc 0.2 v cc
30 mb89628r/629r/p629 (6) peripheral input timing (v cc = +5.0 v 10%, av ss = v ss = 0.0 v, t a = C40 c to +85 c) * : for information on t inst, see (4) instruction cycle. parameter symbol pin condition value unit remarks min. max. peripheral input h pulse width 1 t ilih1 pwc, ec, int0 to int3 2 t inst * m s peripheral input l pulse width 1 t ihil1 2 t inst * m s peripheral input h pulse width 2 t ilih2 adst a/d mode 32 t inst * m s peripheral input l pulse width 2 t ihil2 32 t inst * m s peripheral input h pulse width 2 t ilih2 sense mode 8 t inst * m s peripheral input l pulse width 2 t ihil2 8 t inst * m s 0.2 v cc 0.8 v cc t ihil1 0.8 v cc pwc ec int0 to int3 0.2 v cc t ilih1 0.2 v cc 0.8 v cc t ihil2 0.8 v cc adst 0.2 v cc t ilih2
31 mb89628r/629r/p629 5. a/d converter electrical characteristics (av cc = v cc = +3.5 v to +6.0 v, av ss = v ss = 0.0 v, t a = C40 c to +85 c) * : for information on t inst , see (4) instruction cycle in 4. ac characteristics. (1) a/d glossary ? resolution analog changes that are identifiable with the a/d converter. when the number of bits is 8, analog voltage can be divided into 2 8 = 256. ? linearity error (unit: lsb) the deviation of the straight line connecting the zero transition point (0000 0000 ? 0000 0001) with the full-scale transition point (1111 1111 ? 1111 1110) from actual conversion characteristics ? differential linearity error (unit: lsb) the deviation of input voltage needed to change the output code by 1 lsb from the theoretical value ? total error (unit: lsb) the difference between theoretical and actual conversion values parameter symbol pin condition value unit remarks min. typ. max. resolution 8bit total error avr = av cc 1.5 lsb linearity error 1.0 lsb differential linearity error 0.9 lsb zero transition voltage v ot av ss C 1.0 lsb av ss + 0.5 lsb av ss + 2.0 lsb mv full-scale transition voltage v fst avr C 3.0 lsb avr C 1.5 lsb avr mv interchannel disparity 0.5lsb a/d mode conversion time 44 t inst * m s sense mode conversion time 12 t inst * m s analog port input current i ain an0 to an7 10 m a analog input voltage 0.0 avr v reference voltage avr 0.0 av cc v reference voltage supply current i r avr = 5.0 v, when a/d conversion activated 100 ?m a i rh avr = 5.0 v, when a/d conversion stopped 1 m a
32 mb89628r/629r/p629 (2) precautions ? input impedance of the analog input pins the a/d converter contains a sample hold circuit as illustrated below to fetch analog input voltage into the sample hold capacitor for eight instruction cycles after activating a/d conversion. for this reason, if the output impedance of the external circuit for the analog input is high, analog input voltage might not stabilize within the analog input sampling period. therefore, it is recommended to keep the output impedance of the external circuit low (below 10 k w ). note that if the impedance cannot be kept low, it is recommended to connect an external capacitor of about 0.1 m f for the analog input pin. ?error the smaller the | avr C av ss |, the greater the error would become relatively. v ot v nt v (n + 1)t v fst digital output (1 lsb n + v ot ) 0000 0000 0000 0000 0001 0010 1111 1111 1110 1111 1 lsb = avr 256 linearity error = v nt (1 lsb n + v ot ) 1 lsb differential linearity error = v ( n + 1 ) t ? nt 1 lsb analog input actual conversion value theoretical conversion value ? total error = 1 lsb v nt (1 lsb n + 1 lsb) . . analog input equivalent circuit close for 8 instruction cycles after activating a/d conversion. sample hold circuit c = 33 pf analog channel selector analog input pin r = 6 k w comparator if the analog input impedance is higher than 10 k w , it is recommended to connect an external capacitor of approx. 0.1 m f.
33 mb89628r/629r/p629 n instructions execution instructions can be divided into the following four groups: ? transfer ? arithmetic operation ? branch ?others table 1 lists symbols used for notation of instructions. table 1 instruction symbols (continued) symbol meaning dir direct address (8 bits) off offset (8 bits) ext extended address (16 bits) #vct vector table number (3 bits) #d8 immediate data (8 bits) #d16 immediate data (16 bits) dir: b bit direct address (8:3 bits) rel branch relative address (8 bits) @ register indirect (example: @a, @ix, @ep) a accumulator a (whether its length is 8 or 16 bits is determined by the instruction in use.) ah upper 8 bits of accumulator a (8 bits) al lower 8 bits of accumulator a (8 bits) t temporary accumulator t (whether its length is 8 or 16 bits is determined by the instruction in use.) th upper 8 bits of temporary accumulator t (8 bits) tl lower 8 bits of temporary accumulator t (8 bits) ix index register ix (16 bits)
34 mb89628r/629r/p629 (continued) columns indicate the following: mnemonic: assembler notation of an instruction ~: number of instructions #: number of bytes operation: operation of an instruction tl, th, ah: a content change when each of the tl, th, and ah instructions is executed. symbols in the column indicate the following: ? C indicates no change. ? dh is the 8 upper bits of operation description data. ? al and ah must become the contents of al and ah immediately before the instruction is executed. ? 00 becomes 00. n, z, v, c: an instruction of which the corresponding flag will change. if + is written in this column, the relevant instruction will change its corresponding flag. op code: code of an instruction. if an instruction is more than one code, it is written according to the following rule: example: 48 to 4f ? this indicates 48, 49, ... 4f. symbol meaning ep extra pointer ep (16 bits) pc program counter pc (16 bits) sp stack pointer sp (16 bits) ps program status ps (16 bits) dr accumulator a or index register ix (16 bits) ccr condition code register ccr (8 bits) rp register bank pointer rp (5 bits) ri general-purpose register ri (8 bits, i = 0 to 7) indicates that the very is the immediate data. (whether its length is 8 or 16 bits is determined by the instruction in use.) ( ) indicates that the contents of is the target of accessing. (whether its length is 8 or 16 bits is determined by the instruction in use.) (( )) the address indicated by the contents of is the target of accessing. (whether its length is 8 or 16 bits is determined by the instruction in use.)
35 mb89628r/629r/p629 table 2 transfer instructions (48 instructions) notes: during byte transfer to a, t ? a is restricted to low bytes. operands in more than one operand instruction must be stored in the order in which their mnemonics are written. (reverse arrangement of f 2 mc-8 family) mnemonic ~ # operation tl th ah n z v c op code mov dir,a mov @ix +off,a mov ext,a mov @ep,a mov ri,a mov a,#d8 mov a,dir mov a,@ix +off mov a,ext mov a,@a mov a,@ep mov a,ri mov dir,#d8 mov @ix +off,#d8 mov @ep,#d8 mov ri,#d8 movw dir,a movw @ix +off,a movw ext,a movw @ep,a movw ep,a movw a,#d16 movw a,dir movw a,@ix +off movw a,ext movw a,@a movw a,@ep movw a,ep movw ep,#d16 movw ix,a movw a,ix movw sp,a movw a,sp mov @a,t movw @a,t movw ix,#d16 movw a,ps movw ps,a movw sp,#d16 swap setb dir: b clrb dir: b xch a,t xchw a,t xchw a,ep xchw a,ix xchw a,sp movw a,pc 3 4 4 3 3 2 3 4 4 3 3 3 4 5 4 4 4 5 5 4 2 3 4 5 5 4 4 2 3 2 2 2 2 3 4 3 2 2 3 2 4 4 2 3 3 3 3 2 2 2 3 1 1 2 2 2 3 1 1 1 3 3 2 2 2 2 3 1 1 3 2 2 3 1 1 1 3 1 1 1 1 1 1 3 1 1 3 1 2 2 1 1 1 1 1 1 (dir) ? (a) ( (ix) +off ) ? (a) (ext) ? (a) ( (ep) ) ? (a) (ri) ? (a) (a) ? d8 (a) ? (dir) (a) ? ( (ix) +off) (a) ? (ext) (a) ? ( (a) ) (a) ? ( (ep) ) (a) ? (ri) (dir) ? d8 ( (ix) +off ) ? d8 ( (ep) ) ? d8 (ri) ? d8 (dir) ? (ah),(dir + 1) ? (al) ( (ix) +off) ? (ah), ( (ix) +off + 1) ? (al) (ext) ? (ah), (ext + 1) ? (al) ( (ep) ) ? (ah),( (ep) + 1) ? (al) (ep) ? (a) (a) ? d16 (ah) ? (dir), (al) ? (dir + 1) (ah) ? ( (ix) +off), (al) ? ( (ix) +off + 1) (ah) ? (ext), (al) ? (ext + 1) (ah) ? ( (a) ), (al) ? ( (a) ) + 1) (ah) ? ( (ep) ), (al) ? ( (ep) + 1) (a) ? (ep) (ep) ? d16 (ix) ? (a) (a) ? (ix) (sp) ? (a) (a) ? (sp) ( (a) ) ? (t) ( (a) ) ? (th),( (a) + 1) ? (tl) (ix) ? d16 (a) ? (ps) (ps) ? (a) (sp) ? d16 (ah) ? (al) (dir): b ? 1 (dir): b ? 0 (al) ? (tl) (a) ? (t) (a) ? (ep) (a) ? (ix) (a) ? (sp) (a) ? (pc) C C C C C al al al al al al al C C C C C C C C C al al al al al al C C C C C C C C C C C C C C C al al C C C C C C C C C C C C C C C C C C C C C C C C C ah ah ah ah ah ah C C C C C C C C C C C C C C C C ah C C C C C C C C C C C C C C C C C C C C C C C C C dh dh dh dh dh dh dh C C dh C dh C C C dh C C al C C C dh dh dh dh dh C C C C C C C C C C C C C C C C C C C C + + C C + + C C + + C C + + C C + + C C + + C C + + C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C + + C C + + C C + + C C + + C C + + C C + + C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C + + + + C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C 45 46 61 47 48 to 4f 04 05 06 60 92 07 08 to 0f 85 86 87 88 to 8f d5 d6 d4 d7 e3 e4 c5 c6 c4 93 c7 f3 e7 e2 f2 e1 f1 82 83 e6 70 71 e5 10 a8 to af a0 to a7 42 43 f7 f6 f5 f0
36 mb89628r/629r/p629 table 3 arithmetic operation instructions (62 instructions) (continued) mnemonic ~ # operation tl th ah n z v c op code addc a,ri addc a,#d8 addc a,dir addc a,@ix +off addc a,@ep addcw a addc a subc a,ri subc a,#d8 subc a,dir subc a,@ix +off subc a,@ep subcw a subc a inc ri incw ep incw ix incw a dec ri decw ep decw ix decw a mulu a divu a andw a orw a xorw a cmp a cmpw a rorc a rolc a cmp a,#d8 cmp a,dir cmp a,@ep cmp a,@ix +off cmp a,ri daa das xor a xor a,#d8 xor a,dir xor a,@ep xor a,@ix +off xor a,ri and a and a,#d8 and a,dir 3 2 3 4 3 3 2 3 2 3 4 3 3 2 4 3 3 3 4 3 3 3 19 21 3 3 3 2 3 2 2 2 3 3 4 3 2 2 2 2 3 3 4 3 2 2 3 1 2 2 2 1 1 1 1 2 2 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 2 1 2 1 1 1 1 2 2 1 2 1 1 2 2 (a) ? (a) + (ri) + c (a) ? (a) + d8 + c (a) ? (a) + (dir) + c (a) ? (a) + ( (ix) +off) + c (a) ? (a) + ( (ep) ) + c (a) ? (a) + (t) + c (al) ? (al) + (tl) + c (a) ? (a) - (ri) - c (a) ? (a) - d8 - c (a) ? (a) - (dir) - c (a) ? (a) - ( (ix) +off) - c (a) ? (a) - ( (ep) ) - c (a) ? (t) - (a) - c (al) ? (tl) - (al) - c (ri) ? (ri) + 1 (ep) ? (ep) + 1 (ix) ? (ix) + 1 (a) ? (a) + 1 (ri) ? (ri) - 1 (ep) ? (ep) - 1 (ix) ? (ix) - 1 (a) ? (a) - 1 (a) ? (al) (tl) (a) ? (t) / (al),mod ? (t) (a) ? (a) (t) (a) ? (a) (t) (a) ? (a) " (t) (tl) - (al) (t) - (a) (a) - d8 (a) - (dir) (a) - ( (ep) ) (a) - ( (ix) +off) (a) - (ri) decimal adjust for addition decimal adjust for subtraction (a) ? (al) " (tl) (a) ? (al) " d8 (a) ? (al) " (dir) (a) ? (al) " ( (ep) ) (a) ? (al) " ( (ix) +off) (a) ? (al) " (ri) (a) ? (al) (tl) (a) ? (al) d8 (a) ? (al) (dir) C C C C C C C C C C C C C C C C C C C C C C C dl C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C 00 C C C C C C C C C C C C C C C C C C C C C C C C C C C C dh C C C C C C dh C C C C dh C C C dh dh 00 dh dh dh C C C C C C C C C C C C C C C C C C C C + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + C C C C C C C C C + + C C + + + C C C C C C C C C + + C C C C C C C C C C + + r C + + r C + + r C + + + + + + + + + + C + + + C + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + r C + + r C + + r C + + r C + + r C + + r C + + r C + + r C + + r C 28 to 2f 24 25 26 27 23 22 38 to 3f 34 35 36 37 33 32 c8 to cf c3 c2 c0 d8 to df d3 d2 d0 01 11 63 73 53 12 13 03 02 14 15 17 16 18 to 1f 84 94 52 54 55 57 56 58 to 5f 62 64 65 a c ? ? ?? a c
37 mb89628r/629r/p629 (continued) table 4 branch instructions (17 instructions) table 5 other instructions (9 instructions) mnemonic ~ # operation tl th ah n z v c op code and a,@ep and a,@ix +off and a,ri or a or a,#d8 or a,dir or a,@ep or a,@ix +off or a,ri cmp dir,#d8 cmp @ep,#d8 cmp @ix +off,#d8 cmp ri,#d8 incw sp decw sp 3 4 3 2 2 3 3 4 3 5 4 5 4 3 3 1 2 1 1 2 2 1 2 1 3 2 3 2 1 1 (a) ? (al) ( (ep) ) (a) ? (al) ( (ix) +off) (a) ? (al) (ri) (a) ? (al) (tl) (a) ? (al) d8 (a) ? (al) (dir) (a) ? (al) ( (ep) ) (a) ? (al) ( (ix) +off) (a) ? (al) (ri) (dir) C d8 ( (ep) ) C d8 ( (ix) + off) C d8 (ri) C d8 (sp) ? (sp) + 1 (sp) ? (sp) C 1 C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C + + r C + + r C + + r C + + r C + + r C + + r C + + r C + + r C + + r C + + + + + + + + + + + + + + + + C C C C C C C C 67 66 68 to 6f 72 74 75 77 76 78 to 7f 95 97 96 98 to 9f c1 d1 mnemonic ~ # operation tl th ah n z v c op code bz/beq rel bnz/bne rel bc/blo rel bnc/bhs rel bn rel bp rel blt rel bge rel bbc dir: b,rel bbs dir: b,rel jmp @a jmp ext callv #vct call ext xchw a,pc ret reti 3 3 3 3 3 3 3 3 5 5 2 3 6 6 3 4 6 2 2 2 2 2 2 2 2 3 3 1 3 1 3 1 1 1 if z = 1 then pc ? pc + rel if z = 0 then pc ? pc + rel if c = 1 then pc ? pc + rel if c = 0 then pc ? pc + rel if n = 1 then pc ? pc + rel if n = 0 then pc ? pc + rel if v " n = 1 then pc ? pc + rel if v " n = 0 then pc ? pc + rei if (dir: b) = 0 then pc ? pc + rel if (dir: b) = 1 then pc ? pc + rel (pc) ? (a) (pc) ? ext vector call subroutine call (pc) ? (a),(a) ? (pc) + 1 return from subrountine return form interrupt C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C dh C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C + C C C + C C C C C C C C C C C C C C C C C C C C C C C C C C restore fd fc f9 f8 fb fa ff fe b0 to b7 b8 to bf e0 21 e8 to ef 31 f4 20 30 mnemonic ~ # operation tl th ah n z v c op code pushw a popw a pushw ix popw ix nop clrc setc clri seti 4 4 4 4 1 1 1 1 1 1 1 1 1 1 1 1 1 1 C C C C C C C C C C C C C C C C C C C dh C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C r C C C s C C C C C C C C 40 50 41 51 00 81 91 80 90
38 mb89628r/629r/p629 n instruction map 0123456789abcdef 0 nop swap ret reti pushw a popw a mov a,ext movw a,ps clri seti clrb dir: 0 bbc dir: 0,rel incw a decw a jmp @a movw a,pc 1 mulu a divu a jmp addr16 call addr16 pushw ix popw ix mov ext,a movw ps,a clrc setc clrb dir: 1 bbc dir: 1,rel incw sp decw sp movw sp,a movw a,sp 2 rolc a cmp a addc a subc a xch a, t xor a and a or a mov @a,t mov a,@a clrb dir: 2 bbc dir: 2,rel incw ix decw ix movw ix,a movw a,ix 3 rorc a cmpw a addcw a subcw a xchw a, t xorw a andw a orw a movw @a,t movw a,@a clrb dir: 3 bbc dir: 3,rel incw ep decw ep movw ep,a movw a,ep 4 mov a,#d8 cmp a,#d8 addc a,#d8 subc a,#d8 xor a,#d8 and a,#d8 or a,#d8 daa das clrb dir: 4 bbc dir: 4,rel movw a,ext movw ext,a movw a,#d16 xchw a,pc 5 mov a,dir cmp a,dir addc a,dir subc a,dir mov dir,a xor a,dir and a,dir or a,dir mov dir,#d8 cmp dir,#d8 clrb dir: 5 bbc dir: 5,rel movw a,dir movw dir,a movw sp,#d16 xchw a,sp 6 mov a,@ix +d cmp a,@ix +d addc a,@ix +d subc a,@ix +d mov @ix +d,a xor a,@ix +d and a,@ix +d or a,@ix +d mov @ix +d,#d8 cmp @ix +d,#d8 clrb dir: 6 bbc dir: 6,rel movw a,@ix +d movw @ix +d,a movw ix,#d16 xchw a,ix 7 mov a,@ep cmp a,@ep addc a,@ep subc a,@ep mov @ep,a xor a,@ep and a,@ep or a,@ep mov @ep,#d8 cmp @ep,#d8 clrb dir: 7 bbc dir: 7,rel movw a,@ep movw @ep,a movw ep,#d16 xchw a,ep 8 mov a,r0 cmp a,r0 addc a,r0 subc a,r0 mov r0,a xor a,r0 and a,r0 or a,r0 mov r0,#d8 cmp r0,#d8 setb dir: 0 bbs dir: 0,rel inc r0 dec r0 callv #0 bnc rel 9 mov a,r1 cmp a,r1 addc a,r1 subc a,r1 mov r1,a xor a,r1 and a,r1 or a,r1 mov r1,#d8 cmp r1,#d8 setb dir: 1 bbs dir: 1,rel inc r1 dec r1 callv #1 bc rel a mov a,r2 cmp a,r2 addc a,r2 subc a,r2 mov r2,a xor a,r2 and a,r2 or a,r2 mov r2,#d8 cmp r2,#d8 setb dir: 2 bbs dir: 2,rel inc r2 dec r2 callv #2 bp rel b mov a,r3 cmp a,r3 addc a,r3 subc a,r3 mov r3,a xor a,r3 and a,r3 or a,r3 mov r3,#d8 cmp r3,#d8 setb dir: 3 bbs dir: 3,rel inc r3 dec r3 callv #3 bn rel c mov a,r4 cmp a,r4 addc a,r4 subc a,r4 mov r4,a xor a,r4 and a,r4 or a,r4 mov r4,#d8 cmp r4,#d8 setb dir: 4 bbs dir: 4,rel inc r4 dec r4 callv #4 bnz rel d mov a,r5 cmp a,r5 addc a,r5 subc a,r5 mov r5,a xor a,r5 and a,r5 or a,r5 mov r5,#d8 cmp r5,#d8 setb dir: 5 bbs dir: 5,rel inc r5 dec r5 callv #5 bz rel e mov a,r6 cmp a,r6 addc a,r6 subc a,r6 mov r6,a xor a,r6 and a,r6 or a,r6 mov r6,#d8 cmp r6,#d8 setb dir: 6 bbs dir: 6,rel inc r6 dec r6 callv #6 bge rel f mov a,r7 cmp a,r7 addc a,r7 subc a,r7 mov r7,a xor a,r7 and a,r7 or a,r7 mov r7,#d8 cmp r7,#d8 setb dir: 7 bbs dir: 7,rel inc r7 dec r7 callv #7 blt rel l h
39 mb89628r/629r/p629 n mask options n ordering information no. model mb89628r/ mb89629r mb89p629 mb89pv620 specifying procedure specify when ordering masking set with eprom programmer setting not possible 1 pull-up resistors p00 to p07, p10 to p17, p30 to p37, p40 to p47, p50 to p57, p60 to p64 selectable per pin. (p50 to p57 must be set to without a pull-up resistor when an a/d converter is used.) can be set per pin. (p40 to p47 are available only for without a pull-up resistor.) fixed to without pull-up resistor 2 power-on reset with power-on reset without power-on reset selectable setting possible fixed to with power-on reset 3 oscillation stabilization time selection crystal oscillator: (2 18 /f c ) (26.2 ms/10 mhz) ceramic oscillator: (2 14 /f c ) (1.64 ms/10 mhz) selectable setting possible fixed to crystal oscillator of 2 18 /f c 4 reset pin output with reset output without reset output selectable setting possible fixed to with reset output part number package remarks mb89628rp-sh mb89629rp-sh MB89P629P-SH 64-pin plastic sh-dip (dip-64p-m01) mb89628rpf mb89629rpf mb89p629pf 64-pin plastic qfp (fpt-64p-m06) mb89pv620c-sh 64-pin ceramic mdip (mdp-64c-p02) mb89pv620cf 64-pin ceramic mqfp (mqp-64c-p01)
40 mb89628r/629r/p629 n package dimensions 64-pin plastic sh-dip ( dip -64p-m01) +0.50 C0 C0 +.020 C.022 +.008 C0.55 +0.22 55.118(2.170)ref index-2 15max typ 19.05(.750) (.010.002) 0.250.05 max 1.778(.070) (.070.007) 1.7780.18 1.00 .039 (.018.004) 0.450.10 0.51(.020)min 3.00(.118)min 5.65(.222)max index-1 (.669.010) 17.000.25 2.283 58.00 1994 fujitsu limited d64001s-3c-4 c dimensions in mm (inches)
41 mb89628r/629r/p629 64-pin plastic qfp (fpt-64p-m06) "a" lead no. 64 52 32 0.25(.010) 0.30(.012) 51 33 1 19 20 index typ (.016.004) 0.400.10 1.00(.0394) 0.150.05(.006.002) 18.00(.709)ref 22.300.40(.878.016) (stand off) 0.05(.002)min 3.35(.132)max (.551.008) 14.000.20 (.642.016) 16.300.40 ref 12.00(.472) (.736.016) 18.700.40 20.000.20(.787.008) 24.700.40(.972.016) (.047.008) details of "b" part 1.200.20 0 10 details of "a" part 0.18(.007)max 0.63(.025)max 0.10(.004) "b" m 0.20(.008) 1994 fujitsu limited f64013s - 3c - 2 c dimensions in mm (inches)
42 mb89628r/629r/p629 +0.13 C0.08 +.005 C.003 index area 0~9 (.750.012) 19.050.30 0.46 .018 (2.240.025) (.010.002) 0.250.05 (.050.010) 1.270.25 (.135.015) 3.430.38 55.12(2.170)ref (.035.005) 0.900.13 (.070.010) 1.7780.25 10.16(.400)max 33.02(1.300)ref (.100.010) 2.540.25 (.738.012) 18.750.30 typ 15.24(.600) 56.900.64 1994 fujitsu limited m64002sc - 1 - 4 c 64-pin ceramic mdip (mdp-64c-p02) dimensions in mm (inches)
43 mb89628r/629r/p629 +0.40 C0.20 +.016 C.008 +0.40 C0.20 +.016 C.008 1.20 .047 12.00(.472)typ (.039.010) 1.000.25 typ 18.00(.709) (.039.010) 1.000.25 (.016.004) 0.400.10 1.20 .047 (.016.004) 0.400.10 max 10.82(.426) (.006.002) 0.150.05 0.50(.020)typ 11.68(.460)typ 9.48(.373)typ 7.62(.300)typ 0.30(.012)typ (.050.005) 1.270.13 (.713.008) 18.120.20 typ 14.22(.560) typ 12.02(.473) typ 10.16(.400) typ 24.70(.972) (.878.013) 22.300.33 (.050.005) 1.270.13 typ 0.30(.012) index area 18.70(.736)typ (.642.013) 16.300.33 (.613.008) 15.580.20 1 99 4 f uj it su limited m 6 4 00 4 sc -1- 3 c 64-pin ceramic mqfp (mqp-64c-p01) dimensions in mm (inches)
44 mb89628r/629r/p629 fujitsu limited for further information please contact: japan fujitsu limited corporate global business support division electronic devices kawasaki plant, 1015, kamikodanaka nakahara-ku, kawasaki-shi kanagawa 211, japan tel: (044) 754-3753 fax: (044) 754-3329 north and south america fujitsu microelectronics, inc. semiconductor division 3545 north first street san jose, ca 95134-1804, u.s.a. tel: (408) 922-9000 fax: (408) 432-9044/9045 europe fujitsu mikroelektronik gmbh am siebenstein 6-10 63303 dreieich-buchschlag germany tel: (06103) 690-0 fax: (06103) 690-122 asia pacific fujitsu microelectronics asia pte. limited no. 51 bras basah road, plaza by the park, #06-04 to #06-07 singapore 189554 tel: 336-1600 fax: 336-1609 f9606 ? fujitsu limited printed in japan all rights reserved. circuit diagrams utilizing fujitsu products are included as a means of illustrating typical semiconductor applications. com- plete information sufficient for construction purposes is not nec- essarily given. the information contained in this document has been carefully checked and is believed to be reliable. however, fujitsu as- sumes no responsibility for inaccuracies. the information contained in this document does not convey any license under the copyrights, patent rights or trademarks claimed and owned by fujitsu. fujitsu reserves the right to change products or specifications without notice. no part of this publication may be copied or reproduced in any form or by any means, or transferred to any third party without prior written consent of fujitsu. the information contained in this document are not intended for use with equipments which require extremely high reliability such as aerospace equipments, undersea repeaters, nuclear con- trol systems or medical equipments for life support.

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